The present invention disclosed herein relates to a time to digital converter.
A time to digital converter (TDC) is a circuit block converting time information into digital code. Once a start signal and a stop signal are inputted to a TDC, the TDC measures a time difference between the start signal and the stop signal and outputs it as digital code.
A typical TDC uses a delay line configured with a plurality of delay cells. Such a TDC compares the order of a stop signal and an application time as delaying a start signal by a predetermined time through the delay line. When the delayed start signal is applied later than the stop signal, the delay time of a corresponding start signal becomes a time difference between the start signal and the stop signal and a TDC outputs a digital code corresponding to the delay time.
In relation to a typical TDC, the number of delay cells configuring a delay line is increased in proportional to the number of bits in a digital code. As a result, a time difference between two signals to be converted becomes longer. Moreover, when a time difference is converted into a high resolution, since the number of output bits of a TDC becomes greater, hardware that the TDC requires is required more and also a chip area and power consumption are increased.